Class CacheLine

Namespace

DotCompute.Backends.CUDA.Memory

Assembly

DotCompute.Backends.CUDA.dll

Cache-line padded wrappers for atomic counters in lock-free queues.

public static class CacheLine

Inheritance

object

CacheLine

Inherited Members

object.Equals(object)

object.Equals(object, object)

object.GetHashCode()

object.GetType()

object.MemberwiseClone()

object.ReferenceEquals(object, object)

object.ToString()

Remarks

Two counters that share a cache line ping-pong the line between cores on every access — false sharing — invalidating the entire L1/L2 line. RustCompute's SpscQueue measured a 22–28% throughput improvement after padding producer and consumer counters onto separate cache lines.

Padding is set to 128 bytes to cover modern x86 (Zen 4) and NVIDIA Hopper L2 line widths. On older 64-byte-line CPUs this is a one-line waste per counter, which is negligible.

Fields

Size

Padding size in bytes (128 covers modern Zen and Hopper L2).

public const int Size = 128

Field Value

int